The present invention provides a driver and a receiver circuit for transmitting high-speed data between electronic devices. Specifically, a receiver and associated driver circuit form an interface circuit for transferring data at high speeds between circuit devices.
Battery operated, portable and handheld electronic devices such as, mobile phones, portable entertainment consoles, personal digital assistants (PDAs), global positioning systems (GPS) and gaming devices, are evolving to the point where internal data transfers may occur at rates in excess of 100 megabits per second. It is expected that such portable and handheld devices are likely to require internal data transfers in excess of 1 gigabit per second. These faster data rates represent an increase of 10 to 100 times over current data transfer rates between devices. Background art interfaces operating at gigabit speeds per second consume too much power to be efficiently used in such portable or handheld electronic devices. Thus, background art current mode logic (CML) or low voltage differential signaling (LVDS) interface, as will be explained below, have power/speed performance metrics that would be unsuitable for portable or handheld devices with gigabit data transfer rates.
In addition, a problem associated with transmission paths that transmit such high-speed data is that they produce electromagnetic emissions that can cause electromagnetic interference (EMI) in their environment. The issue of EMI is exasperated by a necessary increase in power consumption for the driver and receiver circuits when they operate at these higher frequencies associated with gigabit data transfer rates.
Background art driver and receiver circuits typically operate over a differential connection that has a 50 ohm impedance transmission line geometry. The differential currents carried by the transmission lines are converted at the receiver to a voltage using a 50 ohm termination impedance. The currents must be large enough so that the voltage developed across the 50 ohm termination impedance is sufficiently above the voltage noise floor to reliably detect the digital signal. Since the standard termination impedance is 50 ohms per line, the transmission of current must be in the order of a few milliamperes in order to produce the few hundreds of millivolts necessary for reliable detection. In the background art CML or LVDS transmitter-receiver standards, a transmission of a current of eight milliamperes is typically required to achieve this result over distances up-to 40 inches. Thus, another problem with background art devices is that the same current level is used regardless of the link distance.
Therefore, there is a need in the art for interface devices with power/speed performance metrics that would be suitable for portable or handheld devices with gigabit data transfer rates and with the ability to adjust current level requirements in accordance with distance in order to further reduce power consumption.